Thuesday January, 22
Session 1 : 14H Dynamic compilation
Chairman : Bruce Childers
- “Automatic Generation of Efficient Dynamic Binary Translators” Luc Michel, Nicolas Fournel and Frédéric Pétrot 2013-DCE-Luc-Michel-article 2013-DCE-Luc-Michel-slides
- “Scaling down to embedded systems for dynamic compilation” Alexandre Carbon, Yves Lhuillier and Henri-Pierre Charles 2013-DCE-Alexandre-Carbon-article 2013-DCE-Alexandre-Carbon-slides
Session 2: 16h30 A Case for Hybrid Microarchitecture (invited presentation)
Chairman : Henri-Pierre Charles Invited talk by Naveen Kumar 2013-DCE-Naveen-Kumar-Keynote Abstract : A Hybrid Microarchitecture is one that leverages hardware/software co-design to couple a dynamic binary translation and optimization software subsystem with a simple, often in-order, microprocessor hardware design. The underlying hardware implements a custom ISA designed specifically to facilitate a software component that manages execution, dynamically translating the instruction stream from a host ISA (e.g. x86) to the custom ISA. The most notable commercial realizations of such hybrid architectures include Transmeta's Crusoe and Efficeon processors. Recently, there has been renewed interest in hybrid microarchitecture, particularly in the research community and these hybrid designs may cause a dramatic shift in how we view and design future architectures. In this talk, I will highlight some recent research work in the area of hybrid microarchitecture. Next, I will discuss several design challenges faced by the microprocessor industry and address how hybrid microarchitecture could be better suited to meet these challenges than the current state-of-the-art. I will also propose research questions that must be addressed in order for hybrid microarchitecture to become mainstream.
Bio: Naveen Kumar is a researcher with Intel Labs in Santa Clara, California. His research interests include microprocessor architecture, dynamic binary translation and virtualization. Naveen's current research at Intel Corporation focuses on Hybrid Microarchitectures. Previously, he worked at VMware on multi-processor record replay techniques, among other things. Naveen has a doctorate from University of Pittsburgh in Pittsburgh, U.S.A., and Bachelors in Technology from Indian Institute of Technology in Varanasi, India.